NAND Flash devices store information as charge in a NAND Flash cell. Multi-level (MLC) NAND flash devices store k bits per cell using 2^k levels of charge. The amount of charge depends on the sequence of k bits being stored. For a certain sequence of k bits, the charge being stored may be distributed within a small range.
FIG. 1 shows an example of a read threshold voltage distribution of 3 bits per cell (bpc) MLC device, the read threshold voltage (voltage level) distribution has eight possible charge distributions (lobes) 11-18. As long as the charge distribution lobes are sufficiently distinct, the cell may be reliably read by using seven read thresholds 21-27.
The voltage level distributions of FIG. 1 illustrates non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. The reason for overlapping may be intentional for obtaining high programming speed, or due to the retention effect. For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there is accumulated trap charge, which is de-trapped over time. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These effects are also known as retention.
Overlap may also occur irrespective of retention. The Flash cells may deteriorate following P/E cycles and the write operation may become less accurate as a result.
The 3 bpc cell includes a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of flash memory module may store three logical pages. This physical page is programmed one logical page after the other. The programming includes various types of programming such as MSB programming (in which some of the cells are programmed to a single lobe and some are left in the erase state. At the end of this programming process only two lobes exists, the erase and the MSB lobes), a CSB programming (in which the erase lobe and the MSB lobe are each split into two lobes by further programming pulses, depending on the original state of each cell and the corresponding CSB bit. At the end of this step there are four lobes) and an LSB programming (in which each of the four lobes is further split to create 8 lobes, overall). The logical pages are read by applying various types of read operations such as MSB read (in which a MSB read threshold is used), CSB read (in which two CSB read thresholds are used) and LSB read (in which four LSB read thresholds are used). FIG. 2 shows similar distributions for the case of 2 bpc devices—the read threshold voltage distribution includes erase lobe 201 and three additional lobes 202-203 that can be read by using read thresholds 211-213. lobes 2.
As mentioned, the lobe distributions are not constant throughout the life of the flash and change with retention and program erase (P/E) cycles. With retention, the distributions become wider and shift towards the erase level. The higher the retention the larger the shift. This effectively shrinks the effective working window. Both the shrinkage of the window and the fattening of the distributions contribute to the increase in number of errors after performing a page read. FIG. 3 illustrates these effects. Just after being programmed the read threshold voltage distribution has eight non-overlapping lobes 111-118 that can be read by read thresholds 121-127 while following retention the read threshold voltage distribution has eight partially overlapping lobes 311-318 that differ from non-overlapping lobes 111-118. Read thresholds 321-327 can be applied when reading lone 311-318 but the number of read errors may exceed error correction coding capabilities.
These effects become significantly worse as the block P/E cycles increase and as the NAND Flash memory technology node shrinks.
The implications of the retention effect is that using the same set of read-read thresholds just following a programming operation and then following retention time may contribute to the number of read errors. In fact, it may be impossible to find a satisfactory set of such read-read thresholds. It is therefore crucial to optimally adjust the read threshold positions to minimize the number of errors.
Typically, a NAND flash controller contains an (Error Correction Code) ECC module so that a relatively small amount of errors due to lobes overlapping and/or due to using sub-optimal read thresholds can be corrected and the data written on the flash can be read. The decoder module which implements the ECC can also say which bits had errors, and whether these errors were of bits which originally had the value ‘1’ but were read as ‘0’ or the other way around.